An electrostatic discharge (ESD) pulse is a sudden and unexpected voltage and/or current discharge that transfers energy to an electronic device from an outside body (e.g., a human body, which can be approximated in modeling by a human body model (HBM)). ESD pulses can damage electronic devices, for example by “blowing out” a gate oxide of a transistor in cases of high voltage or by “melting” an active region area of a device in cases of high current, causing junction failure. If devices are damaged by an ESD pulse, the electronic product can be rendered less operable than desired, or can even be rendered inoperable altogether.
To protect electronic devices from ESD pulses, engineers have developed ESD protection devices. FIG. 1 shows an example of an integrated circuit 100 that includes one or more semiconductor devices 102, which are coupled to an exterior circuit assembly (not shown) via an external IC pin 104. The external IC pin 104 can be a supply pin that supplies a DC supply voltage (e.g., VDD or VSS) to the devices 102, or can be an input/output (I/O) pin that transfers input or output signals there from, for example. A conventional ESD protection device 106 is coupled between the semiconductor device(s) 102 and the external pin 104 to mitigate damage due to an ESD pulse 108. If an ESD pulse 108 occurs, the ESD protection device 106 detects the ESD pulse 108 and shunts the energy associated with it away from the semiconductor device(s) 102 (e.g., as shown by arrow WESD), thereby preventing damage to the semiconductor device(s) 102.
The inventors have appreciated that a conventional ESD protection device 106 suffers from a shortcoming in that it can be inadvertently triggered by harsh circuit conditions (e.g., overvoltage spikes, injection of substrate currents). Such inadvertent triggering can arise in some instances due to the fact that modern system on chip (SoC) designs integrate many different functional blocks onto a single IC. For instance, some mobile phone ICs integrate a digital baseband core with analog blocks like a power management unit, RF transceiver, and mixed signal sub-circuits. These blocks can switch at different frequencies and can each require a different power supply domain. Because of this, operation of one block can cause voltage spikes on its own supply voltage or on the voltage supply of another block. Although these voltage spikes are part of the “normal” operation of the device 102 and are often tolerable in-and-of themselves, these voltage spikes can look like ESD events in some regards. Hence, the voltage spikes can inadvertently trigger the ESD protection device 106. If the ESD protection device 106 is inadvertently triggered, the ESD protection device 106 can shunt normal operating power away from the semiconductor device 102, thereby hampering proper operation of the semiconductor device 102.
In view of the above, the inventors have devised ESD protection techniques that provide adequate ESD protection while concurrently helping to ensure that harsh circuit conditions (e.g., overvoltage spikes) do not inadvertently trigger the ESD device.